The present invention relates to an integrated circuit with multiprocessor architecture.
Microprocessors and DSPs (digital signal processors) are being widely used in many applications. Particularly, in the field of mobile communications under the recent remarkable development, the information processability required is now several times as high as that of a known single processor and thus an architecture in which multiple processors share a memory, or a so-called multiprocessor architecture, has been widely adopted. On the other hand, as the design rule has been reduced, an LSI (large-scale integrated circuit) including multiple processors and a memory that are integrated on a single chip, is now implementable.
FIG. 10 illustrates an example of a known multiprocessor structure. In this example, a first processor 500 and a second processor 510 both access a memory 520 through a memory controller 530 to carry out processing. The first processor 500 includes arithmetic and logic unit (ALU) 501, address output unit 502, clock supply unit 503 and reset control unit 504. Similarly, the second processor 510 includes arithmetic and logic unit (ALU) 511, address output unit 512, clock supply unit 513 and reset control unit 514. The first and second processors 500 and 510 are coupled to the memory 520 through a data bus 540.
In this LSI, first, second and third reset signals RST1, RST2 and RST3 are asserted first, thereby resetting the first and second processors 500 and 510 and memory controller 530, respectively. In the first processor 500, when RST1 is asserted, the reset control unit 504 resets the units 501, 502 and 503 shown in FIG. 10 and units such as one (not shown) in charge of execution and control of instructions, for example. In the second processor 510, when RST2 is asserted, a similar reset operation is performed. The memory controller 530 is reset by RST3. A first clock signal CLK1 is supplied to the first processor 500. A second clock signal CLK2 is supplied to the second processor 510. A third clock signal CLK3 is supplied to the memory 520 and memory controller 530.
Next, when RST1, RST2 and RST3 are negated, the first and second processors 500 and 510, memory 520 and memory controller 530 start their predetermined operations. In this case, the first processor 500 operates synchronously with CLK1. The second processor 510 operates synchronously with CLK2. The memory 520 and memory controller 530 operate synchronously with CLK3. However, CLK1, CLK2 and CLK3 are out of phase with each other. Thus, the first and second processors 500 and 510, memory 520 and memory controller 530 operate asynchronously with each other.
Hereinafter, it will be described how the first processor 500 accesses the memory 520 after the reset operation has been performed.
FIG. 11 is a timing diagram illustrating a case where the first processor 500 reads data from the memory 520. The processor 500 synchronizes with CLK1, and at a time t51, asserts a memory access signal MRW1 so as to indicate a readstate and outputs an address ADRS1. Since MRW1 is asserted, the memory controller 530 selects ADRS1 as an address ADRS to be provided to the memory 520. However, MRW1 and ADRS1 are not synchronized with CLK3. Thus, the memory controller 530 provides a memory access signal MRW and an address ADRS that are synchronized with CLK3, to the memory 520 at a time t52. The memory 520 outputs data to the data bus 540 after a memory access time Δt5 has passed. The arithmetic and logic unit 501 of the processor 500 synchronizes with CLK1 and receives the data from the data bus 540 at a time t53.
FIG. 12 is a timing diagram illustrating a case where the processor 500 writes data on the memory 520. The processor 500 synchronizes with CLK1, and at a time t54, asserts MRW1 so as to indicate a write-state and outputs ADRS1 and data to the memory controller 530 and the data bus 540, respectively. Since MRW1 is asserted, the memory controller 530 selects ADRS1 as an address ADRS to be provided to the memory 520. However, MRW1 and ADRS1 are not synchronized with CLK3. Thus, the memory controller 530 provides MRW and ADRS which are synchronized with CLK3, to the memory 520 at a time t55. The memory 520 receives the data from the data bus 540 at a time t56.
Where the second processor 510 reads or writes data from/on the memory 520, a memory access signal MRW2 output from the second processor 510 is asserted. The memory controller 530 then selects an address ADRS2 supplied from the second processor 510 as an address ADRS to be provided to the memory 520. In the other respects, the same operations are performed.
However, in the known structure, data are not transferred at a high speed between the first or second processor 500 or 510 and the memory 520 due to the phase differences among CLK1, CLK2 and CLK3. For example, to access the memory 520, the first processor 500 needs two cycles of CLK1 (from the time t51 to the time t53) in the memory read transaction shown in FIG. 11 and about three cycles of CLK1 (from the time t54 to the time t56) in the memory write transaction shown in FIG. 12.
In addition, the first processor 500 includes the clock supply unit 503 and reset control unit 504 and the second processor 510 also includes the clock supply unit 513 and reset control unit 514. Thus, where the processors are integrated on a single chip, the total chip area increases.
Further, RST1, RST2 and RST3 have to be asserted or negated synchronously with CLK1, CLK2 and CLK3, respectively. Thus, it has been difficult to design the input timing of the reset signals.